ESP32-S3 Baremetal Support

esp32s3_watchdog.c

The watchdogs the ROM arms on our behalf.

Before jumping into the image at flash offset 0 the ROM starts the RTC watchdog and timer-group 0's watchdog in "flash boot" mode, as insurance against a second-stage bootloader that hangs. An image written straight to offset 0 *is* that second-stage bootloader, so it has to take them down or the board reboots every few hundred milliseconds.

Call disable_watchdogs() first thing in _start().

API

Declared in esp32s3_watchdog.h

Functions

void disable_watchdogs(void);

Stops the RTC and timer-group 0 watchdogs, and puts the super watchdog into hardware auto-feed. Call first thing in _start().

returns
nothing

Source

board/esp32s3_watchdog.c
board/esp32s3_watchdog.c
24 lines
/*
 * Disables the watchdogs the ROM arms before jumping into our image.
 */

#include "esp32s3_watchdog.h"
#include "esp32s3_regs.h"

// Each watchdog sits behind a write-protect register: store the magic key to
// unlock it, write the config, then store anything else to lock it again.
void disable_watchdogs(void)
{
    // The super watchdog cannot be disabled, only fed - so let hardware feed it.
    ESP32S3_REG(RTC_CNTL_SWD_WPROTECT_REG) = RTC_CNTL_SWD_WKEY_VALUE;
    ESP32S3_REG(RTC_CNTL_SWD_CONF_REG)    |= RTC_CNTL_SWD_AUTO_FEED_EN;
    ESP32S3_REG(RTC_CNTL_SWD_WPROTECT_REG) = 0;

    ESP32S3_REG(RTC_CNTL_WDTWPROTECT_REG) = RTC_CNTL_WDT_WKEY_VALUE;
    ESP32S3_REG(RTC_CNTL_WDTCONFIG0_REG)  = 0;
    ESP32S3_REG(RTC_CNTL_WDTWPROTECT_REG) = 0;

    ESP32S3_REG(TIMG0_WDTWPROTECT_REG) = TIMG_WDT_WKEY_VALUE;
    ESP32S3_REG(TIMG0_WDTCONFIG0_REG)  = 0;
    ESP32S3_REG(TIMG0_WDTWPROTECT_REG) = 0;
}
include/esp32s3_watchdog.h— the header, in full
include/esp32s3_watchdog.h
21 lines
/*
 * The watchdogs the ROM arms on our behalf.
 *
 * Before jumping into the image at flash offset 0 the ROM starts the RTC
 * watchdog and timer-group 0's watchdog in "flash boot" mode, as insurance
 * against a second-stage bootloader that hangs. An image written straight to
 * offset 0 *is* that second-stage bootloader, so it has to take them down or
 * the board reboots every few hundred milliseconds.
 *
 * Call disable_watchdogs() first thing in _start().
 */

#ifndef ESP32S3_WATCHDOG_H
#define ESP32S3_WATCHDOG_H

// Stops the RTC and timer-group 0 watchdogs, and puts the super watchdog
// into hardware auto-feed. Call first thing in _start().
// returns: nothing
void disable_watchdogs(void);

#endif // ESP32S3_WATCHDOG_H